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| SSM1N45B SSM1N45B 450V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic ballasts based on half bridge configuration. Features * * * * * * 0.5A, 450V, RDS(on) = 4.25 @VGS = 10 V Low gate charge ( typical 6.5 nC) Low Crss ( typical 6.5 pF) 100% avalanche tested Improved dv/dt capability Gate-Source Voltage 50V guaranteed D ! D S G G! SOT-223 SSM Series ! S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 100C) Drain Current - Pulsed (Note 1) SSM1N45B 450 0.5 0.32 4.0 50 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/C C C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25C) Power Dissipation (TL = 25C) 108 0.5 0.25 5.5 0.9 2.5 0.02 -55 to +150 300 TJ, Tstg TL - Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RJA Parameter Thermal Resistance, Junction-to-Ambient (Note 6b) Typ -- Max 63 Units C/W (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Electrical Characteristics Symbol Parameter TC = 25C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 450 V, VGS = 0 V VDS = 360 V, TC = 125C VGS = 50 V, VDS = 0 V VGS = -50 V, VDS = 0 V 450 ------0.5 ------10 100 100 -100 V V/C A A nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 A VDS = VGS, ID = 250 mA VGS = 10 V, ID = 0.25 A VDS = 50 V, ID = 0.25 A (Note 4) 2.3 3.5 --- 3.0 4.2 3.4 0.7 3.7 4.9 4.25 -- V V S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---185 29 6.5 240 40 8.5 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 360 V, ID = 0.5 A, VGS = 10 V (Note 4,5) VDD = 225 V, ID = 0.5 A, RG = 25 (Note 4,5) -------- 7.5 21 23 36 6.5 0.9 3.2 25 50 55 80 8.5 --- ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 0.5 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 0.5 A, dIF / dt = 100 A/s (Note 4) ------ ---102 0.26 0.5 4.0 1.4 --- A A V ns C Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 75mH, IAS = 1.6A, VDD = 50V, RG = 25 , Starting TJ = 25C 3. ISD 0.5A, di/dt 300A/s, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature 6. a) Reference point of the RJL is the drain lead b) When mounted on the minimum pad size recommended (PCB Mount) (RJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RCA is determined by the user's board design) (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Typical Characteristics ID, Drain Current [A] 10 ID , Drain Current [A] 0 VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : 10 0 150 25 -55 10 -1 Notes : 1. 250 s Pulse Test 2. TC = 25 Notes : 1. VDS = 50V 2. 250s Pulse Test 10 -1 10 0 10 1 10 -1 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 12 RDS(ON) [ ], Drain-Source On-Resistance 8 VGS = 10V VGS = 20V IDR, Reverse Drain Current [A] 10 10 0 6 4 150 25 2 Note : TJ = 25 Notes : 1. VGS = 0V 2. 250 s Pulse Test 0 0 1 2 3 4 5 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = 90V 10 300 VGS, Gate-Source Voltage [V] VDS = 225V VDS = 360V Capacitance [pF] Ciss 8 200 Coss 6 100 Crss Note ; 1. VGS = 0 V 2. f = 1 MHz 4 2 Note : ID = 0.5 A 0 -1 10 10 0 10 1 0 0 1 2 3 4 5 6 7 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Typical Characteristics (Continued) 1.2 3.0 BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.1 RDS(ON), (Normalized) Drain-Source On-Resistance 2.5 2.0 1.0 1.5 1.0 Notes : 1. VGS = 10 V 2. ID = 0.25 A 0.9 Notes : 1. VGS = 0 V 2. ID = 250 A 0.5 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.6 1 10 Operation in This Area is Limited by R DS(on) 0.5 ID, Drain Current [A] ID, Drain Current [A] 3 10 0 10 -1 100 s 1 ms 10 ms 100 ms 1s DC Notes : 0.4 0.3 0.2 10 -2 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse o 0.1 10 -3 10 0 10 1 10 2 10 0.0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature 10 2 D = 0 .5 ZJL(t), Thermal Response 10 1 0 .2 0 .1 0 .0 5 PDM t1 s in g le p u ls e 10 0 0 .0 2 0 .0 1 t2 N o te s : 1 . Z J L (t) = 5 0 /W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T L = P D M * Z J L (t) 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Gate Charge Test Circuit & Waveform 50K 12V 200nF 300nF Same Type as DUT VDS VGS 10V Qgs Qg VGS Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RG 10V VGS RL VDD VDS 90% DUT VGS 10% td(on) t on tr td(off) t off tf Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG 10V tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD ID (t) VDD tp DUT VDS (t) Time (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS * dv/dt controlled by RG * ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 SSM1N45B Package Dimensions SOT-223 0.08MAX MAX1.80 1.75 0.20 3.50 0.20 (0.60) 3.00 0.10 0.65 0.20 +0.04 0.06 -0.02 2.30 TYP (0.95) 4.60 0.25 0.70 0.10 (0.95) 0.25 -0.05 +0.10 (0.60) 0~ 10 1.60 0.20 (0.46) (0.89) 6.50 0.20 Dimensions in Millimeters (c)2004 Fairchild Semiconductor Corporation Rev. A, May 2004 7.00 0.30 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM ImpliedDisconnectTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production (c)2004 Fairchild Semiconductor Corporation Rev. I11 |
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